
Every major computing paradigm shift started with the same unglamorous step: someone had to define how software talks to the hardware. x86 did it for CPUs. CUDA did it for GPUs. Now, a paper accepted to ISCA 2026, the premier venue for computer architecture research, is attempting to do the same for an entirely different class of machine: analog dynamical system hardware. The result is DS-ISA, the first Instruction Set Architecture (ISA) designed specifically for Dynamical System Units (DSUs).
The energy wall no one can ignore
AI's energy problem is no longer abstract. AI is getting more powerful, but it is also racking up a massive energy bill. Some estimates suggest that one maximum-length ChatGPT query can use about twice as much power as an average U.S. home does in one minute. Multiply that by billions of daily queries and you have a crisis in the making.
Unconventional AI's stated goal is to build a new type of computer that uses the laws of physics to perform computation, targeting roughly a 1000x reduction in energy consumption. The core idea is that instead of simulating physics on digital silicon, you let the physics do the computing directly.
The connection to energy efficiency is this: in current von Neumann architecture machines, most energy is consumed shuttling information between memory and computation units, whereas dynamical systems merge computation and memory into the same entity. That collapse of the memory-compute boundary is where the efficiency gains come from.
What is a Dynamical System Unit?
A Dynamical System Unit (DSU) is a piece of hardware where coupled physical elements, think oscillators or analog circuits, spontaneously interact and evolve. In a DSU, coupled physical elements spontaneously interact and evolve toward low-energy equilibrium states within an energy landscape that embeds the targeted problem. The system does not "calculate" an answer in the traditional sense. It physically settles into one.
By leveraging a novel electronic dynamical system, various graph learning challenges have been effectively tackled through a rapid, spontaneous natural annealing process. This method has attracted increasing attention due to its orders-of-magnitude improvements in speed and energy efficiency compared to traditional approaches for inference tasks. The hardware is real, CMOS-compatible, and already being explored at research scale. The missing piece has always been software.
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