Unconventional AI's DS-ISA Wants to Be the CUDA of Physics-Based Computers

Every major computing paradigm shift started with the same unglamorous step: someone had to define how software talks to the hardware. x86 did it for CPUs. CUDA did it for GPUs. Now, a paper accepted to ISCA 2026, the premier venue for computer architecture research, is attempting to do the same for an entirely different class of machine: analog dynamical system hardware. The result is DS-ISA, the first Instruction Set Architecture (ISA) designed specifically for Dynamical System Units (DSUs).

The energy wall no one can ignore

AI's energy problem is no longer abstract. AI is getting more powerful, but it is also racking up a massive energy bill. Some estimates suggest that one maximum-length ChatGPT query can use about twice as much power as an average U.S. home does in one minute. Multiply that by billions of daily queries and you have a crisis in the making.

Unconventional AI's stated goal is to build a new type of computer that uses the laws of physics to perform computation, targeting roughly a 1000x reduction in energy consumption. The core idea is that instead of simulating physics on digital silicon, you let the physics do the computing directly.

The connection to energy efficiency is this: in current von Neumann architecture machines, most energy is consumed shuttling information between memory and computation units, whereas dynamical systems merge computation and memory into the same entity. That collapse of the memory-compute boundary is where the efficiency gains come from.

What is a Dynamical System Unit?

A Dynamical System Unit (DSU) is a piece of hardware where coupled physical elements, think oscillators or analog circuits, spontaneously interact and evolve. In a DSU, coupled physical elements spontaneously interact and evolve toward low-energy equilibrium states within an energy landscape that embeds the targeted problem. The system does not "calculate" an answer in the traditional sense. It physically settles into one.

By leveraging a novel electronic dynamical system, various graph learning challenges have been effectively tackled through a rapid, spontaneous natural annealing process. This method has attracted increasing attention due to its orders-of-magnitude improvements in speed and energy efficiency compared to traditional approaches for inference tasks. The hardware is real, CMOS-compatible, and already being explored at research scale. The missing piece has always been software.

The missing abstraction layer

Here is the problem in plain terms: every DSU chip today requires its own bespoke, hand-crafted programming approach. There is no shared vocabulary, no compiler target, no standard runtime. Mapping high-level AI computational problems onto analog hardware relies on implementation-specific, ad hoc methods. That means every new chip design starts from scratch on the software side, which is a massive barrier to adoption.

Traditional computers rely on an ISA that tells the digital hardware exactly what to do, step by step, using discrete digital instructions. Because a DSU computes by leveraging the continuous physical progression of an interconnected analog system, sequential digital ISAs are fundamentally inadequate here. You cannot just port x86 semantics onto a system that evolves continuously through time.

DS-ISA: 9 instructions to rule them all

By analyzing execution patterns across a wide variety of DSU applications, the paper proposes a unified, composable load-lock-evolve-store execution model. Rather than a rigid linear pipeline, computation is broken into five flexible phases:

• Connect: Dynamically configure system connectivity to allocate resources.
• Load: Set initial states and parameters in the hardware components.
• Lock: Clamp boundary components to fixed values so their physical states remain stable.
• Evolve: Trigger the synchronous, collective physical evolution of all non-locked components.
• Store: Retrieve transient or stabilized states from the system.

The paper demonstrates that an entire dynamical unit can be orchestrated using a minimalist 9-instruction ISA. The key insight behind this minimalism is a label-and-trigger mechanism: labeling commands pre-configure which parts of the hardware are locked, and then a single evolution instruction fires them all simultaneously, letting physics take over from there.

Think of it like setting up dominoes and then flicking the first one. The ISA handles the setup; the hardware handles the fall.

Cascading physics for deep networks

A single-layer analog solver is interesting. A multi-layer one is actually useful for modern AI. To handle high-order computations, the paper explores mechanisms for co-evolution with dependency via a Cascading Node Evolution pattern. In this proposed microarchitecture, node groups are connected sequentially to form a physical pipeline.

In a multi-layer machine learning model, the equilibrium state reached by one evolving dynamical stage serves as the direct physical input that drives the evolution of the next cascading stage. This is the analog equivalent of layer-by-layer forward propagation, except the "computation" at each layer is physical settling, not matrix multiplication.

GPU-inspired multi-tenancy

The paper also tackles a practical engineering problem: how do you share expensive analog hardware across multiple tasks? The proposed microarchitecture draws inspiration from GPUs, organizing nodes and couplings into discrete groups, allowing a single instruction to operate synchronously across an entire group in lockstep.

The controller uses a two-level masking scheme to pull this off:

• Inter-group masks handle macro-level synchronization across hardware blocks.
• Intra-group masks selectively target individual elements for fine-grained configuration.

Using a Parallel Node Evolution pattern, the hardware can be dynamically partitioned to execute multiple independent tasks concurrently, such as running batched inference across different models side-by-side. The paper also shows how fine-grained masking can reclaim scattered unused hardware to reduce fragmentation, and enable wear-leveling to extend chip lifespan.

What this unlocks, and what it does not

The real breakthrough here is not the 9 instructions themselves. It is the existence of a formal compiler target. By offering a concrete proof-of-concept for an ISA and its supporting digital controller, this research lays the foundation for constructing a complete DSU software stack. It proves that high-level applications can be systematically compiled down to the raw physics of room-temperature electronics.

This research is explicitly a proof-of-concept. There is no production compiler, no open-source toolchain, and no hardware chip you can order today. The paper is a formal specification, not a product. What it does do is give the community a shared target to build toward, the same role that the RISC-V ISA spec plays for open hardware, without yet having the surrounding ecosystem.

The work is also bounded by the current state of DSU hardware itself. Analog AI has yet to demonstrate software-equivalent accuracy on models that require many tiles and efficient communication of neural-network activations between them. DS-ISA does not solve the accuracy or scalability problems of analog hardware; it only addresses the programmability gap.

Why ISCA acceptance matters

The acceptance of this work into ISCA signals a pivotal consensus shift within the computer architecture community: physics-based AI accelerators are quickly maturing past the point of isolated circuit novelties, and urgently require formal computer science abstractions to sustain a thriving software ecosystem.

This is the same research group, led by Ang Li and co-authors Chunshu Wu, Ruibing Song, Chuan Liu, and Tong Geng, that has been publishing a steady stream of dynamical system hardware work at top venues including ISCA 2024, ISCA 2025, and MICRO 2025. The DS-ISA paper is the capstone abstraction that ties those hardware efforts together into something programmable. The work is supported by the U.S. Department of Energy, DARPA, and NSF.

No code or open-source implementation has been released alongside the paper. But for anyone building compilers, runtimes, or hardware for physics-based AI accelerators, this is the specification to watch.