Google Completes Open-Source Coral NPU Stack for Always-On Edge AI

Google Research has published the Matrix Execution Unit that completes its open-source 32-bit Coral NPU architecture and released Coral Compiler v1.0. The wider launch includes a simulator, an FPGA reference design, Synaptics silicon and two development boards.

Embedded ML teams often rebuild kernels, quantize models again and adapt to a new compiler for each chip. Coral defines a shared architecture and compilation path intended to carry models from JAX, PyTorch and TensorFlow to compatible edge processors. That could reduce vendor-specific work across wearables, hearables, sensors and small robots, provided implementations support the required operators and runtime features.

The 32-bit pieces line up

TOPS and GOPS describe peak arithmetic rates: one TOPS is one trillion operations per second, while 400 GOPS is 400 billion. Comparisons require the same numerical precision and operation-counting convention. The 10 mW figure is an architecture target rather than a guaranteed board-level measurement; model shape, memory traffic, clock speed, process technology and utilization determine measured performance and power.

Matrix math stays close to the registers

The completed architecture combines four milestones:

• Scalar control: A C-programmable RISC-V front end handles control flow and general-purpose work.
• Vector execution: An RVV v1.0 coprocessor runs SIMD operations across multiple data elements.
• Memory and floating point: A tightly coupled memory subsystem feeds the execution units and supports floating-point workloads.
• Matrix execution: The new Matrix Execution Unit accelerates two-dimensional matrix operations.

Neural networks spend much of their time multiplying matrices and vectors. Mapping those operations onto one-dimensional vector lanes can require repeated loads of weights and activations, consuming energy and memory bandwidth. Coral’s Matrix Execution Unit uses outer-product multiply-accumulate operations and local registers to reuse data while updating a two-dimensional output tile.

Google says the engine can perform 256 multiply-accumulates per cycle. A multiply-accumulate is commonly counted as two operations when vendors calculate TOPS. Keeping intermediate data near the execution unit reduces transfers to larger memories, which supports Coral’s low-power target.

Google positions the completed design for compact transformer models such as Gemma, on-device translation, spatial audio processing, continuous sensor analysis and robot perception. Feasibility still depends on model size, numerical precision, available SRAM and the operators supported by a specific implementation.

The compiler carries the portability

Coral Compiler v1.0 uses MLIR, an infrastructure for progressively translating programs between intermediate representations, and IREE, a compiler and runtime stack for deploying machine-learning models. Its framework front ends accept exported programs from JAX, PyTorch and TensorFlow, although the exact export path and supported operations vary by model.

1. Import the model: Framework front ends convert exported programs into representations such as StableHLO and TOSA.
2. Partition the graph: The compiler assigns supported work to the NPU and retains other operations for the host CPU.
3. Optimize execution: Operator fusion reduces intermediate transfers, while tiling fits matrices into local SRAM and accumulators.
4. Lower the program: The compiler emits Coral scalar instructions, RVV v1.0 vector instructions and matrix operations.
5. Validate the target: Teams can run workloads in the MPACT instruction-level simulator or on the FPGA reference design before committing to silicon.

Unsupported operators can force execution onto the CPU, adding transfers, latency and power consumption. A successful compilation therefore provides only the first checkpoint. Production evaluation needs whole-model traces showing partition boundaries, fallback frequency, memory use and sustained throughput.

Open RTL reaches development boards

The complete 32-bit design is available from the RTL repository for integration into custom chips. VeriSilicon provides design verification and implementation support for tape-outs, while GlobalFoundries offers a path based on its 12LP+ FinFET process.

Synaptics specifically cites Milestone 2 RISC-V Vector support for the SR200. Developers evaluating the new Milestone 4 matrix engine need to confirm which commercial product and configuration implements it. The architecture release, compiler release and currently announced hardware represent separate parts of the Coral program.

Portability has measurable boundaries

Coral’s common toolchain can reduce the amount of platform-specific compiler work, but portability remains bounded by each chip’s architecture milestone, enabled features, memory system, drivers and supported data types. The shared workflow produces target-specific binaries, and every device still requires its own performance and power validation.

Teams evaluating the stack can use a representative production model to check:

• Framework export compatibility and operator coverage
• CPU fallback and host-to-NPU transfer costs
• Quantization, floating-point and mixed-precision support
• Local SRAM capacity and external-memory bandwidth
• End-to-end latency, sustained throughput and measured power
• Runtime, driver and board-support maturity
• RTL, compiler and third-party IP licensing requirements

SoC designers gain an inspectable NPU implementation and a pre-silicon test path. Compiler engineers can inspect and extend the lowering pipeline. Application teams working on always-on perception, audio, anomaly detection and compact transformers gain commercial boards for testing the model workflow.

The next target: 64-bit with CHERI

Google’s roadmap calls for a 64-bit Coral NPU architecture and CHERI-based memory safety. CHERI adds hardware-enforced bounds and permissions to pointers, limiting the memory that code can access. The current release remains the 32-bit architecture, compiler, simulator and FPGA design.

Practical multi-vendor portability will depend on additional silicon providers implementing compatible targets and maintaining their runtimes. The published RTL and compiler, combined with simulation tools and an orderable Coralboard SL, give developers a concrete stack for measuring how well that portability works.